march 2001 copyright ? alliance semiconductor. all rights reserved. as7c4096 AS7C34096 5v/3.3v 512k 8 cmos sram ? 3/23/01; v.1.1 alliance semiconductor p. 1 of 10 features ? as7c4096 (5v version) AS7C34096 (3.3v version) industrial and commercial temperature organization: 524,288 words 8 bits center power and ground pins high speed - 10/12/15/20 ns address access time - 5/6/7/8 ns output enable access time low power consumption: active - 1375 mw (as7c4096) / max @ 12 ns - 468 mw (AS7C34096) / max @ 12 ns low power consumption: standby - 110 mw (as7c4096) / max cmos - 72 mw (AS7C34096) / max cmos 2.0v data retention equal access and cycle times easy memory expansion with ce , oe inputs ttl-compatible, three-state i/o jedec standard packages - 400 mil 36-pin soj - 400 mil 44-pin tsop ii esd protection 2000 volts latch-up current 200 ma logic block diagram 524,288 8 array (4,194,304) sense amp input buffer i/o8 i/o1 oe ce we column decoder row decoder control circuit a0 a1 a2 a3 a4 a5 a6 a7 v cc gnd a8 a10 a11 a12 a13 a14 a15 a16 a17 a18 a9 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 a15 oe i/o8 i/o7 gnd v cc i/o6 i/o5 a14 a13 a12 a11 a10 nc a0 a1 a2 a3 a4 ce /o1 /o2 v cc g nd /o3 /o4 we a5 a6 a7 17 18 a8 a9 36 35 34 33 nc a18 a17 a16 gnd v cc i/o6 i/o5 nc a14 a13 a12 a11 a10 a4 ce i/o1 i/o2 v cc gnd i/o3 i/o4 we a5 a6 a7 a8 a9 i/o8 i/o7 a1 a2 a3 a0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 43 42 41 44 a16 a15 a17 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 2 3 4 1 nc nc nc nc nc nc nc nc nc oe a18 36-pin soj (400 mil) 44-pin tsopii(400 mil) selection guide AS7C34096 ?10 as7c4096 AS7C34096 ?12 as7c4096 AS7C34096 ?15 as7c4096 AS7C34096 ?20 unit maximum address access time 10 12 15 20 ns maximum output enable access time 56 7 9ns maximum operating current as7c4096 ? 250 220 180 ma AS7C34096 160 130 110 100 ma maximum cmos standby current as7c4096 ? 20 20 20 ma AS7C34096 20 20 20 20 ma
? as7c4096 AS7C34096 3/23/01; v.1.1 alliance semiconductor p. 2 of 10 functional description the as7c4096 and AS7C34096 are high-performance cmos 4,194,304-bit static random access memory (sram) devices organized as 524,288 words 8 bits. they are designed for memory applications where fast data access, low power, and simple interfacing are desired. equal address access and cycle times (t aa , t rc , t wc ) of 10/12/15/20 ns with output enable access times (t oe ) of 5/6/7/8 ns are ideal for high-performance applications. the chip enable input ce permits easy memory expansion with multiple-bank memory systems. when ce is high the device enters standby mode. the as7c4096 is guaranteed not to exceed 110 mw power consumption in cmos standby mode. both devices offer 2.0v data retention. a write cycle is accomplished by asserting write enable (we ) and chip enable (ce ). data on the input pins i/o1?i/o8 is written on the rising edge of we (write cycle 1) or ce (write cycle 2). to avoid bus contention, external devices should drive i/o pins only after outputs have been disabled with output enable (oe ) or write enable (we ). a read cycle is accomplished by asserting output enable (oe ) and chip enable (ce ), with write enable (we ) high. the chip drives i/o pins with the data word referenced by the input address. when either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. all chip inputs and outputs are ttl-compatible, and operation is from a single supply voltage. both devices are available in th e industry standard 400-mil 36-pin soj and 44-pin tsop ii packages. absolute maximum ratings note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional oper- ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. truth table key: x = don?t care, l = low, h = high parameter device symbol min max unit vo l t ag e o n v cc relative to gnd as7c4096 v t1 ?1 +7.0 v AS7C34096 v t1 ?0.5 +5.0 v voltage on any pin relative to gnd v t2 ?0.5 v cc +0.5 v power dissipation p d ?1.0w storage temperature (plastic) t stg ?65 +150 c te m p e r a t u r e w i t h v cc applied t bias ?55 +125 c dc current unto output (low) i out ?20ma ce we oe data mode hxx high z standby (i sb , i sb1 ) lhh high z output disable (i cc ) lhl d out read (i cc ) llx d in write (i cc )
? as7c4096 AS7C34096 3/23/01; v.1.1 alliance semiconductor p. 3 of 10 recommended operating condition ? v il min = ?3.0v for pulse width less than t rc /2. dc operating characteristics (over the operating range) 1 capacitance (f = 1mhz, t a = 25 c, v cc = nominal) 2 parameter device symbol min nominal max unit supply voltage as7c4096 v cc (12/15/20) 4.5 5.0 5.5 v AS7C34096 v cc (?10) 3.15 3.30 3.6 v AS7C34096 v cc (12/15/20) 3.0 3.3 3.6 v input voltage as7c4096 v ih 2.2 ? v cc + 0.5 v AS7C34096 v ih 2.0 ? v cc + 0.5 v v il ?0.5 ? ?0.8v ambient operating temperature commercial t a 0? 70 c industrial t a ?40 ? 85 c parameter symbol test conditions device ?10 ?12 ?15 ?20 unit min max min max min max min max input leakage current |i li |v cc = max, v in = gnd to v cc ?1?1?1?1 a output leakage current |i lo | v cc = max, ce = v ih v out = gnd to v cc ?1?1?1?1 a operating power supply current i cc v cc = max, ce < v il f = f max , i out = 0ma as7c4096 ? ? ? 250 ? 220 ? 180 ma AS7C34096 ? 160 ? 130 ? 110 ? 100 standby power supply current i sb v cc = max, ce = v ih f = f max , i out = 0ma as7c4096 ? ? ? 60 ? 60 ? 60 ma AS7C34096 ? 60 ? 60 ? 60 ? 60 i sb1 v cc = max, ce v cc ? 0.2v, v in 0.2v or v in v cc ? 0.2v, f = 0 as7c4096 ? ? ? 20 ? 20 ? 20 ma AS7C34096 ? 20 ? 20 ? 20 ? 20 output voltage v ol i ol = 8 ma, v cc = min ? 0.4 ? 0.4 ? 0.4 ? 0.4 v v oh i oh = ?4 ma, v cc = min 2.4 ? 2.4 ? 2.4 ? 2.4 ? v parameter symbol signals test conditions max unit input capacitance c in a, ce , we , oe v in = 0v 5 pf i/o capacitance c i/o i/o v in = v out = 0v 7 pf
? as7c4096 AS7C34096 3/23/01; v.1.1 alliance semiconductor p. 4 of 10 read cycle (over the operating range) 3,9 key to switching waveforms read waveform 1 (address controlled) 3,6,7,9 read waveform 2 (ce , oe controlled) 3,6,8,9 write cycle (over the operating range) 11 parameter symbol ?10?12?15?20 unit notes min max min max min max min max read cycle time t rc 10 ? 12 ? 15 ? 20 ? ns address access time t aa ?10?12?15?20ns3 chip enable (ce ) access time t ace ?10?12?15?20ns3 output enable (oe ) access time t oe ?5?6?7?8ns output hold from address change t oh 3?3?3?3?ns5 ce low to output in low z t clz 3?3?0?0?ns4, 5 ce high to output in high z t chz ?5?6?7?9ns4, 5 oe low to output in low z t olz 0?0?0?0?ns4, 5 oe high to output in high z t ohz ?5?6?7?9ns4, 5 power up time t pu 0?0?0?0?ns4, 5 power down time t pd ?10?12?15?20ns4, 5 parameter symbol ?10 ?12 ?15 ?20 unit notes min max min max min max min max write cycle time t wc 10 ? 12 ? 15 ? 20 ? ns chip enable (ce ) to write end t cw 7?8?10?12?ns undefined/don?t care falling input rising input address d out data valid t oh t aa t rc current supply oe d out t oe t olz t ace t chz t clz t pu t pd i cc i sb 50% 50% t ohz data valid t rc1 ce
? as7c4096 AS7C34096 3/23/01; v.1.1 alliance semiconductor p. 5 of 10 write waveform 1 (we controlled) 10,11 write waveform 2 (ce controlled) 10,11 data retention characteristics (over the operating range) 13 address setup to write end t aw 7?8?10?12?ns address setup time t as 0?0?0?0?ns write pulse width (oe = high) t wp1 7?8?10?12?ns write pulse width (oe = low t wp2 10 ? 12 ? 15 ? 20 ? ns address hold from end of write t ah 0?0?0?0?ns data valid to write end t dw 5?6?7?9?ns data hold time t dh 0?0?0?0?ns4, 5 write enable to output in high z t wz 05060709ns4, 5 output active from write end t ow 3?3?3?3?ns4, 5 parameter symbol test conditions min max unit v cc for data retention v dr v cc = 2.0v ce v cc ? 0.2v v in v cc ? 0.2v or v in 0.2v 2.0 ? v data retention current i ccdr ? 500 a chip deselect to data retention time t cdr 0?ns operation recovery time t r t rc ?ns input leakage current |i li |?1 a parameter symbol ?10?12?15?20 unit notes min max min max min max min max t aw t ah t wc address we d out t dh t ow t dw t wz t wp t as data valid d in t aw address ce we d out t cw t wp t dw t dh t ah t wz t wc t as data valid d in
? as7c4096 AS7C34096 3/23/01; v.1.1 alliance semiconductor p. 6 of 10 data retention waveform ac test conditions notes 1during v cc power-up, a pull-up resistor to v cc on ce is required to meet i sb specification. 2 this parameter is sampled, but not 100% tested. 3 for test conditions, see ac test conditions . 4t clz and t chz are specified with c l = 5pf as in figure c. transition is measured 500 mv from steady-state voltage. 5 this parameter is guaranteed, but not tested. 6we is high for read cycle. 7ce and oe are low for read cycle. 8 address valid prior to or coincident with ce transition low. 9 all read cycle timings are referenced from the last valid address to the first transitioning address. 10 ce or we must be high during address transitions. either ce or we asserting high terminates a write cycle. 11 all write cycle timings are referenced from the last valid address to the first transitioning address. 12 not applicable. 13 2v data retention applies to commercial temperature range operation only. 14 c = 30pf, except at high z and low z parameters, where c = 5pf. v cc ce t r t cdr data retention mode v cc v dr 2.0v v ih v ih v dr v cc 350w c(14) 320w d out gnd +3.3v figure c: 3.3v output load - output load: see figure b or figure c. - input pulse level: gnd to 3.0v. see figures a, b, and c. - input rise and fall times: 2 ns. see figure a. - input and output timing reference levels: 1.5v. 168w thevenin equivalent: d out +1.728v 255w c(14) 480w d out gnd +5v figure b: 5v output load 10% 90% 10% 90% gnd +3.0v figure a: input pulse 2 ns
? as7c4096 AS7C34096 3/23/01; v.1.1 alliance semiconductor p. 7 of 10 typical dc and ac characteristics 12 supply voltage (v) min max nominal 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc , i sb normalized supply current i cc , i sb ambient temperature ( c) ?55 80 125 35 ?10 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc , i sb normalized supply current i cc , i sb vs. ambient temperature t a vs. supply voltage v cc i cc i sb i cc i sb ambient temperature ( c) ?55 80 125 35 ?10 0.2 1 0.04 5 25 625 normalized i sb1 (log scale) normalized supply current i sb1 vs. ambient temperature t a v cc = v cc (nominal) supply voltage (v) min max nominal 0.8 0.9 1.1 1.2 1.0 1.3 1.4 1.5 normalized access time normalized access time t aa ambient temperature ( c) ?55 80 125 35 ?10 0.8 0.9 1.1 1.2 1.0 1.3 1.4 1.5 normalized access time normalized access time t aa cycle frequency (mhz) 075 100 50 25 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc normalized supply current i cc vs. ambient temperature t a vs. cycle frequency 1/t rc , 1/t wc vs. supply voltage v cc v cc = v cc (nominal) v cc = v cc (nominal) t a = 25 c t a = 25 c output voltage (v) v cc 0 20 60 80 40 100 120 140 output source current (ma) output source current i oh output voltage (v) v cc output sink current (ma) output sink current i ol vs. output voltage v ol vs. output voltage v oh 0 20 60 80 40 100 120 140 capacitance (pf) 0 750 1000 500 250 0 5 15 20 10 25 30 35 change in t aa (ns) typical access time change ? t aa vs. output capacitive loading 00 v cc = v cc (nominal) v cc = v cc (nominal) v cc = v cc (nominal) t a = 25 c t a = 25 c
? as7c4096 AS7C34096 3/23/01; v.1.1 alliance semiconductor p. 8 of 10 package dimensions ordering codes na: not available. package version 10 ns 12 ns 15 ns 20 ns soj 5v commercial na as7c4096-12jc as7c4096-15jc as7c4096-20jc 5v industrial na as7c4096-12ji as7c4096-15ji as7c4096-20ji 3.3v commercial as7c4096-10jc AS7C34096-12jc AS7C34096-15jc AS7C34096-20jc 3.3v industrial na AS7C34096-12ji AS7C34096-15ji AS7C34096-20ji tsop ii 5v commercial na as7c4096-12tc as7c4096-15tc as7c4096-20tc 5v industrial na as7c4096-12ti as7c4096-15ti as7c4096-20ti 3.3v commercial as7c4096-10tc AS7C34096-12tc AS7C34096-15tc AS7C34096-20tc 3.3v industrial na AS7C34096-12ti AS7C34096-15ti AS7C34096-20ti 44-pin tsop ii min(mm) max(mm) a1.2 a 1 0.05 0.15 a 2 0.95 1.05 b 0.30 0.45 c 0.15 (typical) d 18.28 18.54 e 1 10.03 10.16 e 11.56 11.96 e 0.80 (typical) l 0.40 0.60 36-pin soj 400 min(mils) max(mils) a .128 0.148 a 1 0.027 ? a 2 0.102 nom b 0.015 0.020 b 1 0.026 0.032 c 0.007 0.013 d .920 .930 e 0.045 0.055 e 0.400 nom e 0.435 0.445 d e 1234567891011121314 44434241403938 3736 35 34333231 15 16 30 29 17 1819 20 28 2726 25 c l a 1 a 2 e 44-pin tsop ii 0?5 21 24 23 e 1 a b seating plane 22 d pin 1 e e 1 e 2 a2 c a1 b 1 b a e 36-pin soj
? copyright alliance semiconductor corporation. all rights reserved. our three-point logo, our name and intelliwatt are tradema rks or registered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its produ cts at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance?s best data and/or estimates at the time of iss uance. alliance reserves the right to change or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are possible. the inf ormation in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or cus tomer. alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a par- ticular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in alliance? s terms and conditions of sale (which are available from alliance). all sales of alli- ance products are made exclusively according to alliance?s terms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its pro ducts for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all claims arising from such use. ? as7c4096 AS7C34096 3/23/01; v.1.1 alliance semiconductor p. 9 of 10 part numbering system as7c x 4096 ?xx j, t x sram prefix blank: 5v cmos 3: 3.3v cmos device number access time package: j: 400-mil soj t: 400-mil tsop ii temperature ranges: c: commercial, 0 c to 70 c i: industrial, -40 c to 85 c
? as7c4096 AS7C34096 3/23/01; v.1.1 alliance semiconductor p. 10 of 10
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